1. Field of the Invention
The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same.
2. Background Art
In the field of semiconductor device packaging, higher density packaging for semiconductor devices has been in demand, because of a recent need for storing a larger volume of information. With a view to reducing a packaging size, various laminated packaging methods have been developed. Drawing of wirings from a silicon chip, in which a semiconductor circuit is formed, to a device package has been conventionally carried out by means of fine metal wirings. In such an art, the following method is proposed to eliminate a wiring area (for example, Japanese Patent Laid-Open Publication No. 2001-53218; and proceedings of 2001 International Conference on Electronics Packaging, pages 39 to 43).
First, a hole (through-hole) extending through a silicon chip is formed in a signal output electrode part on the silicon chip. Then, the through-hole is filled with a metal material (Al, Cu, and so on) so that an electrode exposed to a lower surface of the silicon chip is formed. Next, an interposer (converter) of approximately the same size as that of the silicon chip is prepared. The electrode on the lower surface of the silicon chip and a signal output electrode of the interposer are connected to each other by a soldered bump. Then, an electrode array on the silicon chip is converted into an electrode array for packaging, and the silicon chip is packaged. When another silicon chip is additionally laminated on the silicon chip, the same method is employed.
However, when a silicon chip and an interposer are connected by a soldered bump, or when silicon chips are connected by a soldered bump, a gap is formed therebetween equal to a thickness of the soldered bump. Thus, a laminated thickness is increased and a reduction of a packaging size cannot be sufficiently achieved. In addition, such a gap deteriorates a heat dissipation of the chip.